Integrated circuits (or chips) typically comprise a silicon substrate and semiconductor devices, such as transistors, formed from doped regions within the substrate. Interconnect structures, formed in parallel-like layers overlying the semiconductor substrate, provide electrical connection between devices to form electrical circuits. Typically, several (e.g., 6-9) interconnect layers (each referred to as an“M” or metallization layer) are required to interconnect the devices in a typical integrated circuit. The top interconnect layer comprises a plurality of pads that serve as attachment points for conductive elements (e.g., bond wires or solder balls) for interconnecting the integrated circuit devices to off-chip external contacts, such as pins or leads of a package structure.
A conventional interconnect system comprises a plurality of substantially vertical conductive vias or plugs and substantially horizontal conductive interconnect layers, with a dielectric layer disposed between two vertically adjacent interconnect layers. Upper level conductive vias interconnect two vertically adjacent interconnect layers. Conductive vias in the first or lowest level interconnect an underlying semiconductor device region to an overlying interconnect layer. The interconnect structures are formed by employing conventional metal deposition, photolithographic masking, patterning and etching techniques.
As integrated circuit devices and interconnect structures shrink, and as the devices carry higher frequency analog signals and higher data rate digital signals, the interconnect structures can disadvantageously add delays to the signal propagation time. Also, the increasing complexity of the devices and the added functionality they provide may require a greater number of interconnect structures or levels. But the conventional interconnect metallization material, e.g., aluminum, severely limits signal speed. Also, the contact resistance between the aluminum interconnect structure and device silicon regions contributes significantly to the total circuit resistance, especially as the number of circuit devices and interconnect structures increases. Finally, as interconnect line widths shrink, it is increasingly difficult to deposit conductive material in openings or windows to form high aspect ratio (i.e., the ratio of the opening depth to the opening diameter) conductive vias.
Given the known disadvantages of aluminum interconnect structures, copper is becoming the interconnect material of choice. Copper is a better conductor than aluminum (with a resistance of 1.7 micro-ohm cm compared to 3.1 micro-ohm cm for aluminum), is less susceptible to electromigration (a phenomenon whereby the aluminum interconnect structure thins and can eventually separate due to the electric field and thermal gradients formed by current flow through the aluminum interconnect), can be deposited at lower temperatures (thereby avoiding deleterious effects on previously formed dopant profiles) and is suitable for use in high aspect ratio applications.
The damascene process is one technique for forming copper interconnect structures for integrated circuit devices. Typically, the copper damascene process integrally forms both the conductive vertical via portion and the conductive horizontal interconnect portion (referred to as a metal runner) of an interconnect or metallization layer. To form a copper damascene structure, a hole or window is formed in a dielectric layer, followed by formation of an overlying trench for the metal runner. A subsequent metal deposition step fills both the opening and the trench, forming a complete metal layer comprising a substantially vertical conductive via and a substantially horizontal conductive runner. A final chemical/mechanical polishing step planarizes the deposited metal with respect to the adjacent surface of the dielectric layer.
An example of a prior art dual damascene process is illustrated in the cross-sectional views of FIGS. 1A-1C during various stages of fabrication. As depicted in FIG. 1A, a dielectric layer 10 is deposited or formed on a lower level interconnect 12. A photoresist layer 16, formed over the dielectric layer 10, is patterned and etched according to conventional techniques to form an opening 18 therein. An anisotropic etch process etches a via hole or window 20 in the dielectric layer 10 through the opening 18. The photoresist layer 16 is removed and replaced by a photoresist layer 30 (see FIG. 1B) that is then patterned and etched to form a trench pattern 32. An anisotropic etch process forms a trench 34 (extending perpendicular to the plane of the paper) and simultaneously extends the opening 18 to an upper surface 36 of the lower level interconnect 12. The hole or window 20 can be formed to stop on the upper surface 36 and expose the lower level interconnect 12 (as shown in FIG. 1B) or alternatively can be over-etched to extend partially into the lower level interconnect 12.
As illustrated in FIG. 1C, the hole 20 and trench 34 are simultaneously filled with a suitable conductive material 40, such as copper. According to standard process techniques, a copper seed layer is first deposited, followed by copper electroplating to fill the hole 20 and the trench 34. The material 40 thus forms a conductive trench 42 and a conductive via 44 in contact with the lower level interconnect 12. Additionally, if the material 40 comprises copper, a barrier layer, such as a tantalum layer and/or a tantalum-nitride layer (or other refractory materials and their nitrides) is deposited in the hole 20 and the trench 34, prior to copper deposition. The barrier layer or layers prevents the diffusion of copper into the surrounding material of the dielectric layer 10. Finally, after deposition, the surface of the dielectric layer 10 is planarizes to remove excess metal 40 from a field region 48 using techniques, such as chemical/mechanical polishing (CMP), that are well known in the art.
A second example of prior art dual damascene structure for integrated circuit devices is shown in FIGS. 2A-2C As depicted in FIG. 2A, multiple material layers are formed on a lower level interconnect 58, including a first etch stop layer 60, a first dielectric layer 62, a second etch stop layer 64, a second dielectric layer 66, and an etch mask 68. The etch mask 68 is patterned and etched to form an opening 70 therein. Using the etch mask pattern, an anisotropic first etch process forms a via opening 72 in the second dielectric layer 66, extending downwardly through the second etch stop layer 64 to the first etch stop layer 60. The etch process is terminated when the etchant reaches the etch stop layer 60. The etch mask 68 is removed, an etch mask 78 (see FIG. 2B) is positioned over the second dielectric layer 66 and masked to form an opening 79, which is larger laterally than the opening 70. A second anisotropic etch process etches a trench 80 in the second dielectric layer 66. Simultaneously, the via opening 72 is extended downwardly by etching through the etch stop layer 60, to contact with the underlying lower level interconnect 58. According to this technique the first etchant has a greater selectivity to the etch stop layer 60 than the second etchant. To complete the damascene process, the mask 78 is removed and the trench 80 and via opening 72 are simultaneously filled with a suitable conductive metal (see FIG. 2C) forming a conductive runner 88 and a conductive via 90 in contact with the lower level interconnect 58. The excess conductive material is removed from a field region surface 92 of the second dielectric layer 66, using techniques such as CMP, as known in the art.
In addition to carrying signals between the semiconductor elements, the interconnect structure, whether fabricated from aluminum or copper, is also required to supply power to the various device elements through a power bus structure. In most integrated circuits the power bus is formed as an additional interconnect layer, including vertical conductive vias and a horizontal interconnect layer. Typically the power bus forms the top level interconnect structure. Disadvantageously, the additional power bus interconnect layer increases the number of mask steps, mask layers and process steps, all contributing to an increased fabrication cost. Further, these additional process steps can lower the device yield as they present opportunities for the occurrence of processing defects.
Since the power bus conducts a relatively high current, as compared with the signal interconnect structures, the power bus interconnect layer generally has a greater width, thickness and pitch than the signal interconnect layers. The power bus is also a source of noise and parasitic capacitance that can disrupt performance of proximate devices and interconnect structures. To limit these effects, the power bus may be isolated from other device structures, with the isolating structures consuming valuable device area.